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Interconnect Open Defects and the Diagnosis Response
Today we’ll discuss one of the most common in modern semiconductors: Interconnect Opens! Ever since the switch from aluminum wiring to copper wiring people have been saying that we will see more open...
View ArticleExploring Yield Learning Using Tester Data
One of the most common assumptions made by product and yield engineers is that systematic defects can be identified using only data from the Automatic Test Equipment (ATE). Depending on the type of...
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Why Chain Fails Suck (And What To Do About Them)
I think that we can all agree that scan chain fails suck. A chain fail is when one or more scan chains in non-operational, that is to say data cannot be accurately shifted through the flip-flops...
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Why Does my Failure Analyses Have so Many No Defect Founds?
The #1 reason in the industry for a lousy Physical Failure Analysis (PFA or FA for short) hit rate is not knowing what the defect is before beginning the PFA. Full Disclosure: I made that up based on...
View ArticleWhat Does Root Cause Really Mean?
I was involved in a discussion today with a colleague on the definition of “root cause” in reference to yield detractors. He was contending that a root cause refers to a type of physical defect in an...
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Correlating Design for Manufacturing Critical Features to Silicon Defects...
This blog post is Part 1 of 2. This post is focused on overlaying DFM violations with the shapes contained in a layout-aware diagnosis report, called a DFM Hit. Part 2 will focus on analyzing a whole...
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Correlating Design for Manufacturing Critical Features to Silicon Defects...
This post is a follow up to Correlating Design for Manufacturing Critical Features to Silicon Defects Using Layout-Aware Diagnosis (Part 1 of 2). In the previous post we explored how one can combine...
View Article4 Ways to Securely Communicate Diagnosis Data Between Foundry and Fabless
In the past decade there has been a widespread transition of semiconductor companies going from Integrated Device Manufacturers (IDM) to Fabless. The reasons for this are many but include: Cost of a...
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Gate Oxide Defects Caused by Antenna Effects
Gate oxide defects, sometimes called pinholes, have long been a meddlesome source of yield loss in semiconductor manufacturing. Oxide weaknesses also have the ability to degrade over time, which means...
View ArticleOverkill: 5 Examples of the Best Type of Yield Loss
Overkill is when a perfectly good die fails testing on an ATE even though it is a functioning part. This is the best type of yield loss because the yield can be recovered almost immediately, without...
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